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Semiconductor
February 1999
CT T ODU MEN E PR PLACE -7747 T 2 OLE RE 0-44 OBS ENDED 1-80 .com MM ications arris l ECO h NO R ntral App entapp@ c Ce : Call or email
HC6094
ADSL Analog Front End Chip
VSSA_RX
D0 (LSB)
PGAI+
PGAO+
VDDA_RX
PGAO-
[ /Title (HC60 94) /Subject (ADSL Analog Front End Chip) /Autho r () /Keywords (Harris Semiconductor, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless Local Loop, PBX, Private Branch Exchan ge, NT1+, CO, Cen-
Features
* 14-Bit 5 MSPS DAC * Programmable Gain Stages * Anti-Aliasing and Reconstruction Filters
Description
The HC6094 performs the Analog processing for the ADSL chip set. The transmit chain has a 14 Bit DAC, a third-order Chebyshev reconstruction filter and a programmable attenuator (-12 to 0dB) capable of driving a 220 differential load. The receiver chain has a high impedance input stage, programmable gain stage (0 to 24dB), additional programmable gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing filter for driving an off-chip A/D.
Laser trimmable thin-film resistors are used to set the filter cutoff frequency and DAC linearity. The transmit and receive signal chains are specified at 65dB MTPR.
Applications
* FDM DMT ADSL * CAP ADSL * EC DMT ADSL * Communications Receiver
Ordering Information
PART NUMBER HC6094IN TEMP. RANGE (oC) -40 to 85 PACKAGE 44 Ld MQFP PKG. NO. Q44.10x10
Pinout
HC6094 (MQFP) TOP VIEW
VDDA_ATT D13 (MSB) GNDD_TX GNDA_TX VDDD_TX
CTLOUT
CTLIN
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
1
44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24
TXO+
TXO-
CLK
D12
VSSA_ATT VDDA_TX VSSA_TX ARTN VDDD_RX CS SDI RST SCLK GNDD__RX GNDA_RX
10
11 23 12 13 14 15 16 17 18 19 20 21 22
PGAI-
RXO-
RXO+
RXI+
RXI-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
4260.2
1
HC6094 Functional Block Diagram
CLK
TRANSMITTER
14
-12 TO 0dB PGA0 TX O
D0-D13
DAC
1ST ORDER 1.1MHz LPF
2ND ORDER 1.1MHz LPF
LATCH SCLK SDI SHIFT REGISTER AND LATCHES CS RST
RXO+
2ND ORDER 1.1MHz LPF
1ST ORDER 1.1MHz LPF
RXI PGA2 -9 TO 18dB PGA1 0 TO 24dB
RECEIVER
PGAI
PGAO
Typical Setup
VSSA_TX
CTLIN 14 D0-D13 CLK DAC
CTLOUT -12 TO 0dB PGA0 1ST ORDER 1.1MHz LPF 2ND ORDER 1.1MHz LPF + TX O
RL = 220
SCLK SDI SHIFT REGISTER AND LATCHES CS RST
VDDD_TX, RX VDDA_TX, RX VSSA_TX, RX GNDD_TX, RX GNDA_RX, TX -9 TO 18dB PGA2 0 TO 24dB PGA1
+5V +5V -5V
+ RXO
RL = 2000
2ND ORDER 1.1MHz LPF
1ST ORDER 1.1MHz LPF
RXI
RECEIVER
PGA IN PGA OUT
2
HC6094
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.18W Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Analog Input Voltage to Ground . . . . . . . . . . . . VDD +0.5, VSS -0.5V Digital Input Voltage to Ground. . . . . . . . . . . . . . . .VDD +0.5V, -0.5V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VDD = 5V, VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for 5% Power Supply. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER OVERALL Supply Currents
IDD ISS ICC
VDD (Note 2) VSS (Note 3) VCC Quiescent, No Load
-
66 -79 0 725
-
mA mA A mW
Power Dissipation DIGITAL INTERFACE Input Voltage Thresholds
PD
VIL VIH
2.7 VIN = 0V VIN = VDD -10.0 -10.0 0.1 T1/2 -10 T1 - 10 T1/2 -5 -
0 0 -
0.8 10.0 10.0 5.0 10 T1 +10 T1/2 +5 100 100
V V A A s ns ns ns ns ns ns
Input Currents
IIL IIH
Serial Clock Period CS Active Before Shift Edge Write Data Valid After Shift Edge CS Inactive After Latch Edge Write Data Hold After Latch Edge DAC Setup Time DAC Hold Time 14-BIT DAC Resolution/Monotonicity Integral Linearity Differential Linearity Max Sample Rate TRANSMITTER OUTPUT Output Drive Differential Output Swing Differential Balance Transmit Output Offset Multi-Tone Power Ratio Power Supply Rejection
T1 T2 T3 T4 T5 tS tH
14 ILE DLE Measured at TX Outputs 4.416
1.5 0.9 -
-
Bits LSB LSB Ms/s
TXOD TXOS TXDB TXOFF TXMTPR PSRR
Sink or Source RL = 220 Gain Match Between Outputs Max Gain Single Ended (Note 4) RL = 220 Input Referred - VDD Input Referred - VSS
30 11.7 -200 40 55
55 12.03 0.5 25 65 65 84
12.3 200 -
mA VPP % mV dB dB dB
3
HC6094
Electrical Specifications
VDD = 5V, VSS = -5V, RL Open, Over Temperature Range; Unless Otherwise Specified. Designed for 5% Power Supply. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER TRANSMITTER GAIN STAGE Gain Error
TXPG
RL = 220, 0dB Setting RL= 220, Each Step Relative to 0dB
-0.22 -0.15
+0.02 0.02
0.22 0.15
dB dB
TRANSMITTER FREQUENCY RESPONSE Gain Ripple Peak to Peak Stopband Attenuation Floor Attenuation GP GS GM Across 1.104MHz Bandwidth At 2.65MHz At 9.94MHz 14 0.2 17 58 0.6 dB dB dB
RECEIVER INPUT (PGA1 AND PGA2) Input Swing Input Impedance RXIS RXRIN Differential PGA1 PGA2 Common Mode Rejection Common Mode Range Continuous Input Voltage RECEIVER OUTPUT (INCLUDING PGA1 OUT) Differential Output Swing RXOS RXOUT (RL = 2000) PGA1OUT (RL = 2000) Differential Balance PGA1 Output Offset PGA2 Output Offset Multi-Tone Power Ratio Power Supply Rejection RXDB RXOFF RXOFF RXMTPR PSRR End to End (RXIN to RXOUT) Max Gain Single Ended (Note 4) Max Gain Single Ended (Note 4) RL = 2000 Input Referred - VDD Input Referred - VSS RECEIVER GAIN STAGE Absolute Gain Error RXPG Any Step (RXIN to RXOUT) -0.3 0.01 0.3 dB 12.0 12.0 -200 -200 45 55 15.8 16.0 0.5 40 30 65 69 84 200 200 VPP VPP % mV mV dB dB dB RXCMRR RXCMIR 1.1MHz 1.0 1.0 -0.25 VSS-0.5 12 90 12 0.25 VDD +0.5 VPP M k dB V V
RECEIVER FREQUENCY RESPONSE Gain Ripple Peak to Peak Stopband Attenuation Floor Attenuation GP GS GM Across 1.104MHz Bandwidth At 2.65MHz At 9.94MHz 14 0.4 19.4 53 0.6 dB dB dB
TRANSMITTER AND RECEIVER FILTER CUTOFF FREQUENCY TX Filter FC RX Filter FC NOTES: 2. VDD = 5V typical, supply range 5%. 3. VSS = -5V typical, supply range 5%. 4. Single ended operation for reference only. Probed to these limits, but not packaged tested. TXFC RXFC -0.15dB point -0.15dB point 1.104 1.104 1.18 1.125 1.25 1.16 MHz MHz
4
HC6094 Definitions
1. Supply currents/power dissipation measured in a quiescent (static) state with RL open. 2. Logic input levels and timing are verified by using them as conditions for testing DAC and filter. 3. Digital input currents are measured at 0V and VCC. 4. DAC resolution and monotonicity guaranteed by ILE and DLE tests. 5. DAC ILE is relative to best fit straight line. 6. Output drive current is the output current at 0V for each output when they are driven to Full Scale. 7. Output offset measured with VIN = 0V differential for the RX, and the DAC at mid scale for the TX. 8. PSRR is the change in differential input voltage vs. change in supply voltage at DC. 9. TX Gain is calculated as 20*Log((TXoutDACFS - TXoutDACZS)/12V) at DC. 10. RX input swing is verified by using this as condition for gain testing. 11. RX Input Impedance is calculated as VIN/IIN where VIN is the maximum input voltages, with the PGA set to 0dB. 12. RX CMRR is calculated as 20*Log(VOUT/VIN)-PGA Gain. VIN is set to 250mVPEAK (CMIR) at 1.1MHz, and PGA gain is set to maximum. 13. RX Gain is calculated as 20*Log(dVOUT/dVIN), where VIN is set to give a nominal Output Swing, or the maximum input swing, whichever is smaller. It is tested DC. 14. Filter Gain/Attenuation is relative to low frequency passband gain. TX tested by driving the DAC (with sinX/X correction), RX tested by driving PGA2. Wafer probe will use special test points to bypass the DAC for laser trimming. 15. MTPR - (Multi-Tone Power Ratio). A DMT waveform is generated which has a specific crest factor or peak to average ratio (PAR) with specific carriers missing. The waveform is then passed through the TX or RX chain. The total integrated power of the notch at the location of the missing carriers is measured with respect to the adjacent carriers. Notch depth is measured for several DMT waveforms with different PARs. The notch depths for each DMT waveform are averaged to give an MTPR number.
5
HC6094 Shift Register Format
Each write operation to a control register involves 16 bits of data. The CS- signal must be enabled low during any serial write operation. The data on SDI shall be clocked in during
CS-
the rising edge of SCLK. A3-A0 supply the address of the control register, and D7-D0 supply the data.
SCLK
SDI
0
A0
A1
A2
A3
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 1. SERIAL CONTROL
Logic Timing Definitions
CS
SCLK t2 t1 t4
SCLK
SDI t3 t5
FIGURE 2. SERIAL INTERFACE
CLK
DAC DATA
tS
tH
FIGURE 3. DAC INTERFACE
6
HC6094 Shift Registers Format
REGISTER RX Gain TX Gain A0 1 0 A1 0 0 A2 X X A3 X X TX PGA0 GAIN D2 1 1 1 0 0 0 0 D1 1 0 0 1 1 0 0 D0 X 1 0 1 0 1 0 RX PGA1 GAIN D3 0 0 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 X D1 0 0 1 1 0 0 1 1 X D0 0 1 0 1 0 1 0 1 X GAIN IN dB 0 3 6 9 12 15 18 21 24 GAIN IN dB -12 -10 -8 -6 -4 -2 0 D0 D1 PGA0 Gain D2 D3 D4 D5 D6 D7 PGA1 Gain PGA2 Gain
NOTE: PGA1 is an inverting amplifier. RX PGA2 GAIN D7 0 0 0 0 0 0 0 0 1 1 D6 0 0 0 0 1 1 1 1 X X D5 0 0 1 1 0 0 1 1 X X D4 0 1 0 1 0 1 0 1 0 1 GAIN IN dB -9 -6 -3 0 3 6 9 12 15 18
Filter Mask Template
AVERAGE PASSBAND GAIN GP -GP
GS
GM 1.104 2.65 9.94 FREQUENCY (MHz)
7
HC6094 Pin Descriptions
PIN NUMBER 43, 44 1-12 13, 14 15 16 17, 18 19, 20 21, 22 23 24 25 26 27 28 29 30 31 32 33 34, 35 36 37 38 PIN NAME D13-D12 D11-D0 RXO VSSA_RX VDDA_RX PGAI PGAO RXI GNDA_RX GNDD_RX SCLK RST SDI CS VDDD_RX ARTN VSSA_TX VDDA_TX VSSA_ATT TXO VDDA_ATT GNDA_TX CTLOUT PIN DESCRIPTION Digital Input bits 13 and 12. D13 is MSB. Digital Input bits 11 thru 0. D0 is LSB. Receiver differential outputs. Receiver -5V supply. Receiver +5V supply. PGA2 differential inputs. PGA1 differential outputs. Receiver differential inputs (PGA1 inputs). Receiver ground. Serial interface ground. Serial interface clock pin. Serial interface reset pin. Serial interface data input. Serial interface chip select. Shift register Digital +5V supply. Analog return (ground). Transmitter -5V supply. Transmitter +5V supply. Attenuator -5V supply. Transmitter differential outputs. Attenuator +5V supply. Analog ground for transmitter. Control Amplifier Output. Provides precision control of the current sources. Typically connected to CTLIN. Input to the Current Source Base Rail. Typically connected to CTLOUT. Requires a 0.1F capacitor to VSSA_TX. Allows external decoupling of the current sources. Digital Ground. DAC input latch clock. DAC digital +5V supply.
39
CTLIN
40 41 42
GNDD_TX CLK VDDD_TX
8
HC6094 Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D D1 -D-
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.004 0.077 0.012 0.012 0.510 0.390 0.510 0.390 0.026 44 0.032 BSC MAX 0.093 0.010 0.083 0.018 0.016 0.530 0.398 0.530 0.398 0.037 MILLIMETERS MIN 0.10 1.95 0.30 0.30 12.95 9.90 12.95 9.90 0.65 44 0.80 BSC MAX 2.35 0.25 2.10 0.45 0.40 13.45 10.10 13.45 10.10 0.95 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 1/94 NOTES:
0.10 0.004
-AE E1
-B-
B B1 D D1 E
e
PIN 1 SEATING A PLANE
E1 L N e
-H-
0.40 0.016 MIN 0o MIN
5o-16o 0.20 A-B S 0.008 M C A2 A1
-CDS B B1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING
1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions.
0o-7o
L
5o-16o
0.13/0.23 0.005/0.009
9

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